1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for aligning wafers by determining an offset between a die grid and a reference point external to the die grid.
2. Description of the Related Art
During the manufacture of semiconductor devices, semiconductor wafers, each including a plurality of individual die, are subjected to a number of processing steps. Typically, wafers are grouped into lots that are processed together. Each lot may contain, for example, 25 individual wafers. Certain of the processing steps are sensitive to the alignment of the wafer within the processing tool. For example, photolithography processing steps are highly sensitive to the alignment of the wafer. Other steps, including metrology steps, are also sensitive to wafer alignment, but to differing degrees.
FIG. 1 illustrates a typical semiconductor wafer 100. The wafer 100 includes an orientation notch 110 useful as a reference point for a rough alignment of the wafer 100. For identification purposes, a unique wafer identification code 120 is scribed on the wafer 100 beneath the notch 110 using a laser scribing process where small dots are burned into the surface of the wafer to construct the characters or symbols of the code. Exemplary wafer identification codes 120 may include alphanumeric identifiers or bar code identifiers (e.g., 1 or 2 dimensional codes). During the production process, process history and metrology information is stored in a database for each of the wafers 100 indexed by its respective wafer identification code 120.
Typically, prior to performing an orientation-sensitive process, the wafer 100 is rotated until the notch 110 is located and placed in a predetermined position. Other techniques for performing rough alignments include using an edge alignment procedure where the wafer 100 is rotated and optically scanned to determine the profile of the edge at various positions about the rotation. Typically, a wafer 100 is not perfectly round. As such, the edge moves with respect to a fixed reference point as the wafer 100 is rotated. By determining the edge profile, the approximate center of the wafer 100 can be determined. The spatial relationship between the notch 110 and the approximate center point may be then used as a reference point for rough alignment of the wafer.
These rough alignment techniques are not suitable for highly sensitive processes such as photolithography. Accordingly, grid reference marks 130 are etched into the wafer 100 prior to the commencement of process steps for forming devices on the wafer 100. A wafer 100 typically includes a plurality of individual semiconductor die arranged in a grid 140. Photolithography steps are typically performed by a stepper on approximately one to four die locations at a time, depending on the specific photomask employed. The grid reference marks 130 are typically located in two designated cells of the grid 140 (i.e., functioning devices are not formed in the designated grid cells). The grid reference marks 130 provide an accurate reference point for aligning the stepper to the individual cells in the grid 140 that are to be exposed. The stepper includes sensitive optical scanning equipment to locate the grid reference marks 130 and finely align the wafer 100 based on the grid reference marks 130 such that the individual cell(s) are accurately patterned.
A typical process for forming the grid reference marks 130 includes forming an initial layer of photoresist, commonly referred to as the zero layer, on the wafer 100. The stepper receives the wafer 100 and performs a rough alignment using the notch and possibly a wafer edge alignment process. After the rough alignment, the stepper exposes the cells designated for the grid reference marks 130 to set the anchor points for the grid 140. The zero layer is then developed, the grid reference marks 130 are etched into the wafer 100, and the zero layer is removed. The stepper then uses the grid reference marks 130 to align all subsequent photolithography exposures.
While the grid reference marks 130 do provide an accurate means for aligning to specific portions of the grid 140, the may only be employed by tools that have the expensive optical scanning devices necessary to detect them. Other tools, such as metrology tools, are not equipped with such circuitry, and thus rely on less accurate alignment techniques. Due to wafer edge profile variations, the grid 140 is not always oriented using a predetermined relationship with respect to the notch or approximate center point. The less expensive techniques that align based on an external reference point (e.g., the approximate center of the wafer 100 or the notch 110) can only approximate the relationship between the grid 140 and the external reference point. Hence, because the operations performed by the tools employing an external reference point are less accurately aligned, the results provided by the tool may be less accurate or repeatable.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for aligning wafers. The method includes defining a grid on a wafer; determining a grid offset parameter based on an offset between the grid and an external reference point defined on the wafer; and aligning the wafer based on the grid offset parameter and the external reference point.
Another aspect of the present invention is seen in a system for aligning wafers including a database server and a tool. The database server is adapted to store a grid offset parameter associated with a wafer. The grid offset parameter defines an offset between a grid defined on the wafer and an external reference point defined on the wafer. The tool is adapted to align the wafer based on the grid offset parameter associated with the wafer and the external reference point.